Optimal Architectures

A digital filter implemented in software is typically run on a
processor with a single computational element. This forces
the filter to be implemented in a serial sum-of-products. A
FIR is implemented as a single sum-of-products and an IIR
is typically a sum of products for the feed-forward section
and another sum-of-products for the feedback section.
Hardware can be optimized for each application. Low speed
and low power can be achieved using a bit-serial
implementation. Moderate speed and power may call for a
single parallel multiplier-accumulator. High speed
applications can utilize multiple multiplier-accumulator
structures with specialized memory address schemes.
Decimating or interpolating filters can use optimized
polyphase structures, multiple stages and specialized
memory addressing schemes. Coefficient memory can be
designed to take advantage of coefficient characteristics and
accumulators can be custom-designed to take advantage of
unity gain properties.